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asahi kasei [ak4516a] m0026-e-00 - 1 - ak4516a 3v 16bit adc&dac with built-in pga feature 1 . resolution: 16 bits 2 . recording function analog input pga (programmable gain amp) peak-meter output overflow flag output auto limitter circuit auto recovery circuit hpf(fc=3.4hz) for offset cancel 3 . playback function ? digital de-emphasis filter(tc=50/15us, fs=32khz, 44.1khz, 48khz) 4 . analog-through mode 5 . power management 6 . adc input (including the pga) single-ended input input level: 1.7vpp (=0.57 va , va =3 v ) thd+n: -85db dr,s/n: 90db 7 . dac output single-ended output output level: 1.8vpp (=0.6 va, va=3v, r l 3 10k w ) frequency response: 0.5db( ~ 20khz) thd+n: -86db dr,s/n: 90db 8 . master clock: 256fs/384fs 9 . audio data format adc: 16bit, msb first, msb justified, iis, lsb justified(only bick=64fs correspondent) dac: 16bit, msb first, msb justified, iis, msb justified 10 . ta: -20 ~ 85 c 11 . power supply: 2.5 ~ 3.6v 12 . power dissipation: 18ma 13 . 24pinvsop (0.65mm pitch)
asahi kasei [ak4516a] m0026-e-00 1998/08 - 2 -
asahi kasei [ak4516a] m0026-e-00 1998/08 - 3 - ? ordering guide AK4516AVF -20 ~ +85 c 24pin vsop(0.65mm pitch) akd4516a evaluation board ? pin layout
asahi kasei [ak4516a] m0026-e-00 1998/08 - 4 - pin/function no. pin name i/o function 1 agnd - analog ground pin 2 va - analog power supply pin, +3v 3 rin1 i rch #1 input pin 4 lin1 i lch #1 input pin 5 rin2 i rch #2 input pin 6 lin2 i lch #2 input pin 7 pd i reset & power down pin 8 mclk i master clock input pin 9 lrck i input/output channel clock pin 10 bclk i audio serial data clock pin 11 sdto o audio serial data output pin 12 sdti i audio serial data input pin 13 dgnd - digital ground pin 14 vd - digital power supply pin, +3v 15 cs i chip select pin 16 cclk i control clock input pin 17 cdto o control data output pin 18 cdti i control data input pin 19 dzf o zero detect pin 20 lout o lch analog output pin 21 rout o rch analog output pin 22 vcml o lch common voltage output pin, 0.5 x va don't be connected with external circuit. 23 vcmr o rch common voltage output pin, 0.5 x va don't be connected with external circuit. 24 vcom o common voltage output pin, 0.5 x va don't be connected with external circuit.
asahi kasei [ak4516a] m0026-e-00 1998/08 - 5 - absolute maximum rating (agnd,dgnd=0v; note 1 ) parameter symbol min max units power supplies: analog digital vd-va va vd d vda -0.3 -0.3 - 6.0 6.0 0.3 v v v input current (any pin except supplies.) iin - 10 ma analog input voltage lin1,lin2,rin1,rin2 vina -0.3 va+0.3 v digital input voltage vind -0.3 va+0.3 v ambient temperature ta -20 85 c storage temperature tstg -65 150 c note 1 . all voltage with respect to ground. recommended operating conditions (agnd,dgnd=0v; note1 ) parameter symbol min typ max units power supplies analog digital va vd 2.5 2.5 3.0 3.0 3.6 va v v note 1 . all voltage with respect to ground
asahi kasei [ak4516a] m0026-e-00 1998/08 - 6 - analog characteristics (ta=25 c ; va,vd=3.0v; fs=44.1khz; signal frequency=1khz; measurement frequency=10hz ~ 20khz ; s/(n+d), dr, s/n are specification toward full scale.signal; unless otherwise specified) parameter min typ max units input pga(ipga) characteristics: input voltage(lin1,lin2,rin1,rin2=0.57xva)(note2 ) 1.53 1.7 1.87 vpp input resistance 25 40 60 k w mic line step size +28db ~ -8db -8db ~ -32db -32db ~ -40db -40db ~ -52db +8.0db ~ -28db -28db ~ -52db -52db ~ -60db -60db ~ -72db 0.1 0.1 0.1 0.1 0.5 1 2 4 db db db db adc analog input characteristics : (note 3 ) resolution 16 bits s/(n+d) (-2db input) 75 85 db dr (-60db input, a-weighted) 84 90 db s/n (a-weighted) 84 90 db interchannel isolation 80 90 db interchannel gain mismatch 0.2 0.5 db dac analog output characteristics:(note 4 ) resolution 16 bits s/(n+d) 75 86 db dr (-60db output, a-weighted) 84 90 db s/n (a-weighted) 84 90 db interchannel isolation 90 100 db interchannel gain mismatch 0.1 0.3 db output voltage (aout=0.6 x va) (note 2 ) 1.62 1.8 1.98 vpp load resistance 10 k w power supply power supply: va+vd normal operation (pd="h") ad+da (pm0=1,pm1=1,pm2=1,pm3=0) ad (pm0=1,pm1=1,pm2=0,pm3=0) da (pm0=0,pm1=0,pm2=1,pm3=0) power-down-mode(pd="l") (note 5 ) 18 11 9 10 27 17 14 100 ma ma ma ua note 2 . analog input and output voltage (full-scale voltage:0db) scale with va. ipga: 0.57 x va(typ.), dac : 0.6 x va(typ). 3 . adc is input from lin1/rin1 or lin2/rin2 and it measures included in ipgl/ipgr. the value of ipgl/ipgr is set 0db. internal hpf removes offset in the adc, ipgl/ipgr. 4 . measured by ad725c(shibasoku), rms mode. 5 . in case of the power-down mode, all digital input pins including clock(mclk, bclk, lrck) pins are held vd or dgnd.
asahi kasei [ak4516a] m0026-e-00 1998/08 - 7 - filter characteristics (ta=25 c ; va,vd=2.5 ~ 3.6v; fs=44.1khz; dem bit="0") parameter symbol min typ max units adc digital filter (lpf): passband (note 6 ) 0.1db -0.55db -1.2db pb 0 19.0 20.0 16.5 khz khz khz stopband sb 26.0 khz passband ripple pr 0.1 db stopband attenuation sa 68 db group delay (note 7 ) gd 16.1 1/fs group delay distortion d gd 0us adc digital filter (hpf): frequency response (note 6 ) -3.0db -0.5db -0.1db fr 3.4 10 22 hz hz hz dac digital filter: passband (note 6 ) 0.1db -6.0db pb 0 22.05 20.0 khz khz stopband sb 24.1 khz passband ripple pr 0.06 db stopband attenuation sa 43 db group delay (note 7 ) gd 14.7 1/fs dac digital filter + analog filter frequency response 0 ~ 20.0khz fr 0.5 db note 6 .the passband and stopband frequencies scale with fs (system sampling rate). for example, adc is pb=0.431*fs(@-0.55db), dac is pb=0.454*fs(@-0.1db). 7 .the calculating delay time which occurred by digital filtering. this time is from the input of analog signal to setting the 16 bit data of both channels to the output register for adc. for dac, this time is from setting the 16 bit data of both channels on input register to the output of analog signal.
asahi kasei [ak4516a] m0026-e-00 1998/08 - 8 - dc characteristics (ta=25 c ; va,vd=2.5 ~ 3.6v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 70%vd - - - - 30%vd v v high-level output voltage (iout=-400ua) low-level output voltage (iout=400ua) voh vol vd-0.4 - -- 0.4 v v input leakage current iin - - 10 ua switching characteristics (ta=25 c ; va,vd=2.5 ~ 3.6v; c l =20pf) parameter symbol min typ max units control clock frequency master clock (mclk) 256fs: pulse width low pulse width high 384fs: pulse width low pulse width high fclk tclkl tclkh fclk tclkl tclkh 7.68 28 28 11.52 23 23 11.2896 16.9344 12.8 19.2 mhz ns ns mhz ns ns channel select clock(lrck) frequency duty fs 30 45 44.1 50 50 55 khz % audio interface timing bclk period bclk pulse width low pulse width high lrck edge to bclk " - " bclk " - " to lrck edge lrck to sdto(msb) delay time bclk " " to sdto delay time sdti latch hold time sdti latch set up time tblk tblkl tblkh tlrb tblr tlrm tbsd tsdh tsds 312.5 130 130 50 50 50 50 80 80 ns ns ns ns ns ns ns ns ns control interface timing cclk period cclk pulse width low pulse width high cdata latch set up time cdata latch hold time cs high level time cs " " to cclk " - " cclk " - " to cs " - " cdto output delay time cs " - "to cdto(hi-z)time (note 8 ) tcck tcckl tcckh tcds tcdh tcsw tcss tcsh tdcd tccz 200 80 80 50 50 150 50 50 70 70 ns ns ns ns ns ns ns ns ns ns reset timing pd pulse width pd " - " to sdto delay time tpdw tpdv 150 8224 ns 1/fs note 8 .rl=1k w /10% change (pull-up operates for vd)
asahi kasei [ak4516a] m0026-e-00 1998/08 - 9 - ? timing diagram data input timing in write
asahi kasei [ak4516a] m0026-e-00 1998/08 - 10 - reset timing
asahi kasei [ak4516a] m0026-e-00 1998/08 - 11 - operation overview ? system clock the clocks which are required to operate are mclk(256fs/384fs), lrck(fs), bclk(32fs ~ ). the master clock (mclk) should be synchronized with lrck but the phase is free of care. the mclk can be input 256fs or 384fs. when 384fs is input, the internal master clock is divided into 2/3 automatically. *fs is sampling frequency. all external clocks (mclk, bclk, lrck) should always be present whenever ipga or adc or dac is in operation. if these clocks are not provided, the ak4516a may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. if the external clocks are not present, the ak4516a should be in the power-down mode. (please refer to the "mode control 1" section.) ? system reset ak4516a should be reset once by bringing pd pin "l" upon power-up. the internal timing starts clocking by lrck " - " after exiting reset by mclk. after the system reset operation, the all internal ak4516a registers are initial value. ? zero detection when the input data at both channels are continuously zeros for 8192 lrck cycles, dzf goes to "h". dzf immediately goes to "l", if the input data are not zero. when the dac is power-down, dzf becomes to "l". ? digital high pass filter(hpf) the adc has hpf for the dc offset cancel. the cut-off frequency of hpf is 3.4hz(@fs=44.1khz) and it is -0.1db at 22hz. it also scales with the sampling frequency(fs).
asahi kasei [ak4516a] m0026-e-00 1998/08 - 12 - ? audio serial interface format data is shifted in/out the sdti/sdto pins using bclk and lrck inputs. four serial data are selected by the dif0 and dif1 pins as shown in table 1 . in all modes, the serial data is msb-first, 2's compliment format and it is latched by " - " of bclk. when dif1="0" and dif0="1", only bclk=64fs is acceptable. no. dif1 dif0 sdto(adc) sdti(dac) bclk figure 0 0 0 msb justified lsb justified 3 32fs figure 1 reset 1 0 1 lsb justified lsb justified = 64fs figure 2 2 1 0 msb justified msb justified 3 32fs figure 3 31 1 i 2 s compatible i 2 s compatible 3 32fs figure 4 table 1 . audio data format figure 2. audio data timing (no.1)
asahi kasei [ak4516a] m0026-e-00 1998/08 - 13 - figure 4. audio data timing (no.3)
asahi kasei [ak4516a] m0026-e-00 1998/08 - 14 - ? control register r/w timing the data on the 4 wires serial interface consists of op-code(3bit), address(lsb-first, 5bit) and control data (lsb-first, 8bit). the transmitting data is output to each bit by " " of cclk, the receiving data is latched by " - " of cclk. writing data becomes effective by " - " of cs. reading data becomes hi-z(floating) by " - " of cs. cs should be held to "h" at no access. in case of connecting between cdti and cdto, the i/f can be also controlled by 3-wires. cclk always needs 16 edges of " - " during cs ="l". reading/writing of the address except 00h ~ 0dh are inhibited. reading/writing of the control registers by except op0=op1="1" are invalid. op0- op2: op- code (111:write, 110:read) a0- a4: address d0- d7: control data figure 5 . control data timing
asahi kasei [ak4516a] m0026-e-00 1998/08 - 15 - init: initializing. at this time, zfipl and zfipr are "0". when these flags becomes "1", init process has completed. pd: power-down state. adc is output "0", analog output of dac goes floating. init-1: initializing all registers. init-2: initializing read only registers in control registers. inhibit-1: inhibits writing and reading to all control registers. inhibit-2: enable writing to control registers except "mode control 1 (01h)" register. inhibit-3: enable reading from control registers. inhibit-4: enable writing to only "mode control 1 (01h)" register of the control registers. note: please refer to "explanation of register" about the condition of each register. 1 { digital output corresponding to analog input and analog output corresponding to digital input have the group delay(gd). 2 { if the analog signal does not be input, the digital outputs have the offset to the op-amp of input and some offset error of the internal adc. 3 { a few noise occurs at the " - " of pd signal. please mute the analog output externally if the noise influences the system application. 4 { when the external clocks are stopped, the ak4516a should be in the power-down mode. figure 6 .power-up/power-down timing example
asahi kasei [ak4516a] m0026-e-00 1998/08 - 16 - ? operation mode explanation the ak4516a can perform the limitter operation and the recovery operation automatically. there are three operation modes. 1. manual mode the manual mode is used when the ak4516a mode is changed (for example, when the input pin or the de- emphasis etc setting is changed) or the recording level is adjusted from up writing operation by manual. in case of the semi-auto or the full-auto modes, it is impossible to set up a part of the register. (refer to "semi-auto mode", "full-auto mode" section).
asahi kasei [ak4516a] m0026-e-00 1998/08 - 17 - 2. semi-auto mode the semi-auto mode is the mode that uses the ak4516a auto limitter function, and the recovery operation is processed by up or dsp etc. during the semi-auto mode, writing to the following registers from up is inhibited. lrga, ltm1-0, zelm, lmth1-0, lmat2-0 figure 7 . control example of semi-auto mode operation(lmat = 1 step, zenm=zelm="1") 1 { setting up the registers for the semi-auto mode operation. (ltm1-0, zelm, lmth1-0, lmat2-0, ipgl, ipgr, lrga="1", gsel) 2 { wr(lmte="1", rcve="0"): after the registers concerned in the auto limitter operation is set up and confirming the zero crossing flags(zfipl,zfipr)="1", lmte is set "1". 3 { as the input signal of adc exceeds lmth, the auto limitter operation starts. 4 { wr(ipga="31h"):as the auto limitter is in operation, writing by up is ignored. 5 { after the zero crossing operation of both lch and rch is completed, the next operation starts. 6 { rd(lcdet&ipga):confirm to complete auto limitter operation and reads the ipga present value. 7 { wr(ipga="2fh"):update ipga value. 8 { wr(lmte="0") 9 { in figure 7 , since "0" is written to lmte during att operation, the operation changes to manual mode after completing att operation. after confirming lcdet="1", it is possible to change the each register set-up. if lmte is set "0" during the auto limitter operation or the update of the ipga value by up, lcdet becomes "1" after the max "1" att/gain operation is completed by internal state. 10 { in this case, the input signal of adc exceeds lmth, the auto limitter does not operate because of lmte="0".
asahi kasei [ak4516a] m0026-e-00 1998/08 - 18 - figure 8 register set-up sequence at semi-auto mode
asahi kasei [ak4516a] m0026-e-00 1998/08 - 19 - 3. full-auto mode the full-auto mode is done automatically by the auto limitter and the auto recovery function of the ak4516a. however, writing to the register is needed to enable these functions. during the full-auto mode, writing to the following registers from up is inhibited. lrga, ltm1-0, zelm, lmth1-0, lmat2-0, wtm1-0, nrtm1-0, ratt1-0, zenm, ref6-0, ipgl, ipgr figure 9 . control example of full-auto mode operation (lmat=ratt: 1 step, zenm=zelm="1") 1 { set-up the registers of full-auto mode (ltm1-0, zelm, lmth1-0, lmat2-0, wtm1-0, ratt1-0, nrtm1-0, zenm, ref6-0, gsel, ipgl, ipgr, lrga="1") 2 { wr(lmte=rcve="1"): after the registers concerned in the auto limitter operation is set up and confirming the zero crossing flags(zfipl, zfipr)="1", lmth and rcve are set "1". 3 { wr(ipga="31h"):as the operation is full-auto mode, writing by up is ignored. 4 { the ready of recovery starts. 5 { as the input signal of adc exceeds lmth, the recovery operation (in the figure, recovery ready) is discontinued and the limitter operation starts. 6 { wr(lmte=rcve="0"):the full-auto mode operation is completed. 7 { in figure 9 , since "0" is written to lmte& rcve during the att operation, the operation changes to the manual mode after completing att operation. after confirming lcdet="1", it is possible to change the each register set-up. if lmte&rcve are set "0" during the full-auto mode operation, lcdet becomes "1" after the max "1" att/gain operation is completed by internal state. 8 { in this case, the input signal of adc exceeds lmth, the auto limitter does not operate because of lmte=rcve="0". 9 { after the limitter operation is completed, the ak4516a waits for the time set by wtm1-0. if the input signal does not exceed (lmth - 2db), the recovery operation is executed. after the waiting time finishes the next waiting time starts immediately. in recovery ready, the waiting timer is reset under the condition of (lmth - 2db) input signalinput signal.
asahi kasei [ak4516a] m0026-e-00 1998/08 - 20 - figure 10 . registers set-up sequence at full-auto mode
asahi kasei [ak4516a] m0026-e-00 1998/08 - 21 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h input select 0 0 0 0 rin2 rin1 lin2 lin1 01h mode control 1 0 0 0 0 pm3 pm2 pm1 pm0 02h mode control 2 mono1 mono0 dif1 dif0 fs1 fs0 dem 0 03h zero cross & timer control lrga gsel nrtm1 nrtm0 zenm ltm1 ltm0 zelm 04h peak hold low byte lch pll7 pll6 pll5 pll4 pll3 pll2 pll1 pll0 05h peak hold high byte lch pul7 pul6 pul5 pul4 pul3 pul2 pul1 pul0 06h peak hold low byte rch plr7 plr6 plr5 plr4 plr3 plr2 plr1 plr0 07h peak hold high byte rch pur7 pur6 pur5 pur4 pur3 ur2 pur1 pur0 08h overflow status zfipr zfipl rof2 rof1 rof0 lof2 lof1 lof0 09h auto lmt&rcv control lmte rcve 0 lmth1 lmth0 lmat2 lmat1 lmat0 0ah input pga control lch lcdet ipgl6 ipgl5 ipgl4 ipgl3 ipgl2 ipgl1 ipgl0 0bh input pga control rch lcdet ipgr6 ipgr5 ipgr4 ipgr3 ipgr2 ipgr1 ipgr0 0ch auto recovery control 1 0 0 0 0 wtm1 wtm0 ratt1 ratt0 0dh auto recovery control 2 0 ref6 ref5 ref4 ref3 ref2 ref1 ref0 table 2 . ak4516a register map input select addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h input select 0 0 0 0 rin2 rin1 lin2 lin1 r/w r/w reset 00000101 lin2-1 : select on/off of lch input (0:off, 1:on). these bits can select to on/off at the same time. rin2-1: select on/off of rch input (0:off, 1:on). these bits can select to on/off at the same time. this register is reset at pd pin="l", then inhibits writing to this register.
asahi kasei [ak4516a] m0026-e-00 1998/08 - 22 - mode control 1 addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h mode control 1 0 0 0 0 pm3 pm2 pm1 pm0 r/w r/w reset 00000111 pm3-0: power management (0: power down, 1:power up) pm0: mixer, pga input, auto limitter and auto recovery power control. pm1: power control of adc pm2: power control of dac pm3: used both as power control of analog loopback circuit and as selection of mux. (0: dac, 1:analog loopback) pm0-3 can be partially powered-down by on/off of pm0-3. when pd pin goes "l", all the circuit in ak4516a can be powered-down regardless of pm0-3. when pm0-3 go all "0", all the circuits in ak4516a can be also powered-down. when pm3 goes "1", input for output-amp is selected to analog loopback circuit from dac output. output mux and amp are powered-down when pd ="l" or pm2=pm3="0". refer to figure 11 . the loopback output and the mux selecting dac output is a mixer with the switch in practice. therefore, when both pm2 and pm3 select on, the analog loopback signal and dac output are mixed by gain 1. except the case of pm0=pm1=pm2=pm3="0" or pd pin="l", mclk, bclk, lrck should not be stopped. when the input pga and mux are powered-down by pm0-3 or pd pin, the output of amp becomes hi-z(floating). this register is reset by the pd pin="l", then inhibits writing to this register.
asahi kasei [ak4516a] m0026-e-00 1998/08 - 23 - figure 11 . power management
asahi kasei [ak4516a] m0026-e-00 1998/08 - 24 - mode control 2 addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h mode control 2 mono1 mono0 dif1 dif0 fs1 fs0 dem 0 r/w r/w r/w r/w r/w r/w r/w r/w rd reset 00000000 mono1-0:monaural mixing 00: stereo (reset) 01: (l+r)/2 10: ll 11: rr dif1-0: select audio serial interface format the data is all 2's complement, msb first. no. dif1 dif0 sdto(adc) sdti(dac) bclk figure 0 0 0 msb justified lsb justified 3 32fs figure 1 reset 1 0 1 lsb justified lsb justifed = 64fs figure 2 2 1 0 msb justified msb justified 3 32fs figure 3 31 1 i 2 s compatible i 2 s compatible 3 32fs figure 4 table 3 . audio serial interface format fs1-0:select de-emphasis frequency the ak4516a includes the digital de-emphasis filter(tc=50/15us) by iir filter. the filter corresponds to three sampling frequency (32khz, 44.1khz, 48khz). the de-emphasis filter selected by fs0 and fs1 registers are enabled for input audio data. fs1 fs0 mode 0 0 44.1khz reset 01 off 1 0 48khz 1 1 32khz table 4 . de-empahsis frequency dem: control of de-emphasis (0: disable, 1: enable) fs0 and fs1 registers of the de-emphasis are enabled by setting dem=1. fs0 and fs1 are ignored at dem=0. this register is reset by the pd pin="l", then inhibits writing to this register.
asahi kasei [ak4516a] m0026-e-00 1998/08 - 25 - zero cross & timer control addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h zero cross & timer control lrga gsel nrtm1 nrtm0 zenm ltm1 ltm0 zelm r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 11100100 lrga: selects the method of writing to ipga 0: independent data can be written to ipga and ipgr. 1: common data can be written to ipgl and ipgr. in this case, when a data is written to ipgl, the same data is also written to ipgr. when a data is written to ipgr, a data is only written to ipgr. when ipgl value differs from ipgr value, ipgl and ipgr values can be set by a common data after writing ipgl value at lrga="1". (reset) gsel:selects input gain (set a common lch and rch) 0: line 1: mic (reset) even if line and mic are the same data value, both gain values are different. nrtm1-0: zero crossing timeout at writing operation by up and auto recovery operation. set-up zero crossing timeout at writing operation by up and the auto recovery operation. the writing operation by up and the auto recovery operation set up in common. in case of the auto limitter operation, zero crossing operation is set by different bits(ltm1-0). zero crossing timeout(zenm="1") nrtm1 nrtm0 48khz 44.1khz 32khz 0 0 513/fs 10.7ms 11.6ms 16.0ms 0 1 1025/fs 21.4ms 23.2ms 32.0ms 1 0 2049/fs 42.7ms 46.5ms 64.0ms reset 1 1 4097/fs 85.4ms 92.9ms 128.0ms table 5 . zero crossing timeout at up writing operation and auto recovery operation. (nrtm1="1", nrtm0="0" at reset) zenm: enables zero crossing detection at up write operation or auto recovery operation (0: disable, 1: enable) 1: when ipga of each l/r channels do zero crossing or timeout independently, the ipga value is changed by up write operation or auto recovery operation. 0: ipga is changed immediately.
asahi kasei [ak4516a] m0026-e-00 1998/08 - 26 - ltm1-0:zero crossing timeout(zelm="1") or update period(zelm="0") at the auto limitter mode (ltm1="1", ltm0="0"@reset) zero crossing timeout(zelm="1") update period(zelm="0") lt m 1 lt m 0 48khz 44.1khz 32khz 48khz 44.1khz 32khz 0 0 129/fs 2.7ms 2.9ms 4.0ms 1/fs 21us 23us 31us 0 1 258/fs 5.4ms 5.9ms 8.1ms 2/fs 42us 45us 63us 1 0 516/fs 10.8ms 11.7ms 16.1ms 4/fs 83us 91us 125us 1 1 1032/fs 21.5ms 23.4ms 32.3ms 8/fs 167us 181us 250us table 6 . zero crossing timeout or update period at the auto limitter mode zelm: enables zero crossing detection at the auto limitter operation (0: disable, 1: enable) 0: the ipga value is changed immediately. when the ipga value is changed continuously, the change is done by the period specified by ltm1-0. 1: when ipga of each l/r channel do zero crossing or timeout independently, the ipga value is changed by auto limitter operation. these bits are reset by pd pin="l", then inhibits writing to these bits. peak hold addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h peak hold low byte lch pll7 pll6 pll5 pll4 pll3 pll2 pll1 pll0 05h peak hold high byte lch pul7 pul6 pul5 pul4 pul3 pul2 pul1 pul0 06h peak hold low byte rch plr7 plr6 plr5 plr4 plr3 plr2 plr1 plr0 07h peak hold high byte rch pur7 pur6 pur5 pur4 pur3 pur2 pur1 pur0 r/w rd reset 00h pll7-0: peak hold of lch (absolute value), 8bit of lsb (ffh ~ 00h) pul7-0: peak hold of lch (absolute value), 8bit of msb (7fh ~ 00h) plr7-0: peak hold of rch (absolute value), 8bit of lsb (ffh ~ 00h) pur7-0: peak hold of rch (absolute value), 8bit of msb (7fh ~ 00h) the peak is held l/r audio data independently. these registers are reset by reading 8bit of msb, reading 8bit of both msb and lsb should be continuity controlled by reading in order of 8 bit of msb from lsb. after reading the 8 bit of lsb the last, 8 bit of msb is lost by reading 8 bit of lsb the last. sign bits (pul7, pur7) becomes "0" as the output value is the absolute value. these registers are reset on the following any conditions. pd pin="l" pm1="0"
asahi kasei [ak4516a] m0026-e-00 1998/08 - 27 - overflow status addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h overflow status zfipr zfipl rof2 rof1 rof0 lof2 lof1 lof0 r/w rdrdrdrdrdrdrdrd reset 00000000 zfipr: rch ipga zero crossing detection flag. zfipl: lch ipga zero crossing detection flag. at writing operation by up, when zenm is "1", this flag becomes "0" if ipga value is set independently for l/r. when each channel does zero crossing or timeout, and then ipga of each channel is changed, the flag of each channel becomes "1". when writing to the same channel is done again under zero crossing waiting before this flag becomes "1", the timeout counter is not reset. therefore then, zero crossing timeout period becomes shorter for the new writing. but if writing is done to the channel which the flag is "1" when the flag of either lch or rch is "0", the timeout counter is reset. in this case, zero crossing timeout counter restarts from the last writing. when zeip is "0", zfipl/zfipr always become "1". zfipl/zfipr always become "1" during semi-auto mode operation (lmte="1", rcve="0") and full-auto mode operation (lmte=rcve="1"). zfipr/zfirl is "0" during initializing operation after exiting power-down by pd pin. the completion of the initializing operation can be recognized by confirming these flags are "1". these bits are reset on the following any conditions. pd pin="l" in case of pm0="0", these flag become "1". rof2-0: overflow flag of rch overflow flag includes 3 bit. max value of the overflow is held. these bits are reset to (0, 0, 0) by reading by up. these bits are reset on the following any conditions. pd pin="l" pm1="0" rof2 rof1 rof0 threshold 000 < -12.04db 001 -12.04db 010 -8.52db 011 -6.02db 100 -4.08db 101 -1.80db 110 -0.00db table 7 . overflow flag of rch
asahi kasei [ak4516a] m0026-e-00 1998/08 - 28 - lof2-0: overflow flag of lch overflow flag includes 3bit. max value of overflow is held. these bits are reset to (0, 0, 0) by reading by up. these bits are reset on the following any conditions. pd pin="l" pm1="0" lof2 lof1 lof0 threshold 0 0 0 <-12.04db 001 -12.04db 010 -8.52db 011 -6.02db 100 -4.08db 101 -1.80db 110 -0.00db table 8 . overflow flag of lch
asahi kasei [ak4516a] m0026-e-00 1998/08 - 29 - auto limitter control during the auto limitter operation, when either lch or rch exceed auto limitter detection level (lmth1-0), ipga value is attenuated by auto limitter att step (lmat1-0) automatically. then the ipga value is changed commonly for l/r channels. in this operation, either zero crossing detection with timeout or immediate change is selected by zelm. timeout period and update period are set by ltm1-0 (refer to table 6 ). the operation for attenuation is done continuously until the input signal level becomes lmth1-0 or less. unless lmte is set "1" after finishing operation for attenuation, this operation for attenuation repeats when input signal level exceeds lmth1-0 again. ipga value of register is always written to current value in this mode automatically, the operation for attenuation always starts from current ipga value. when the operation for attenuation is completed after the input signal becomes lmth1-0 or less, auto limitter detection flag(lcdet) becomes "1". this flag become "0" when the input signal exceeds lmth1-0 again and the ak4516a enters the auto limitter operation. during the auto limitter operation (lcdet=0), ipga is changed according to the value set by the auto limitter operation. therefore, up writing operation is ignored. during semi-auto mode and after completing auto limitter operation(lcdet="1"), ipga is changed according to the value written by up. addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h auto lmt&rcv control lmte rcv 0 lmth1 lmth0 lmat2 lmat1 lmat0 r/w r/w r/w rd r/w r/w r/w r/w r/w reset 00011000 lmte: auto limitter enable flag 0: auto limitter operation off (reset) 1: auto limitter operation on rcve: auto recovery enable flag 0: auto recovery operation off(reset) 1: auto recovery operation on. this bit is only available at lmte="1". when lmte is "0" , auto recovery operation becomes "off". the change of operation mode by lmte and rcve bits always needs to control via manual-mode, between the semi-auto mode and the full-auto mode should not be changed. ipga value of each channel should be equal value before entering the semi-auto mode and the full-auto mode. lrga should be set "1" during the semi-auto mode and writing operation by up s hould always write equal value to each channel. lmth1-0:auto limitter detection level / auto recovery waiting counter reset level lmth1 lmth0 auto limitter detection level auto recovery waiting counter reset level 00 adc input 3 -8.0db -8.0db>adc input 3 -10.0db 01 adc input 3 -6.0db -6.0db>adc input 3 -8.0db 10 adc input 3 -4.0db -4.0db>adc input 3 -6.0db 11 adc input 3 -2.0db -2.0db>adc input 3 -4.0db table 9 . auto limitter detection level / auto recovery waiting counter reset level (lmtj1=lmth0="0"@reset)
asahi kasei [ak4516a] m0026-e-00 1998/08 - 30 - lmat2-0: auto limitter att step during the auto limitter operation, when either lch or rch exceeds the auto limitter detection level set by lmth1-0, the number of steps attenuated from current ipga value is set. for example, when the current ipga value is 68h in the state of lmat2-0="111", it becomes ipga=60h by the auto limitter operation, the input signal level is attenuated by 4db (=0.5db x 8). auto limitter operation period is the constant period by setting ltm1-0 at zelm="1", it is the different period by the input signal at zelm="0". (depend on zero crossing detection period) when the attenuation value exceeds ipga="00"(mute), it clips to "00". lmat2 lmat1 lmat0 att step 0 0 0 1 reset 001 2 010 3 011 4 100 5 101 6 110 7 111 8 table 10 . auto limitter att step setting these bits are reset by pd pin="l", then inhibits writing to these bits. input analog pga control addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah input pga control lch lcdet ipgl6 ipgl5 ipgl4 ipgl3 ipgl2 ipgl1 ipgl0 0bh input pga control rch lcdet ipgr6 ipgr5 ipgr4 ipgr3 ipgr2 ipgr1 ipgr0 r/w rd r/w reset 1 30h lcdet: auto limitter and auto recovery detection flag(refer to figure 7 and figure 9 ) 0: updating ipga value by up writing at the semi-auto mode and the auto limitter or the auto recovery operation. 1: complete the auto recovery operation or the auto limitter operation. complete updating ipga value by up writing at semi-auto mode. (reset) this flag(lcdet) always become "1" at manual mode(lmte=rcve="1"). the lcdet in 0ah and 0bh shows the same value. this flag is "0" during initialization after exiting power-down mode by pd pin. during the semi-auto mode operation, if lmte is set "0" during the auto limitter operation or the update of the ipga value by up, lcdet becomes "1" after the max "1" att/gain operation is completed by internal state. during the full-auto-mode operation, if lmte&rcve are set "0" during the full-auto mode operation, lcdet becomes "1" after the max "1" att/gain operation is completed by internal state. in case of changing the registers relative to the semi-auto mode and the full-auto mode, these registers should be changed after writing lmte="0"(at the semi-auto mode) or lmte=rcve="0" (at the full-auto mode) and then confirming lcdet="1".
asahi kasei [ak4516a] m0026-e-00 1998/08 - 31 - ipgl6-0: lch input analog pga. 105 levels. ipgr6-0: rch input analog pga. 105 levels. on/off of zero crossing detection is controlled by zenm/zelm bits. gain(db) data mic line step level 68h +28.0 +8.0 67h +27.5 +7.5 66h +27.0 +7.0 ::: 30h 0.0 -20.0 2fh -0.5 -20.5 ::: 21h -7.5 -27.5 reset 20h -8.0 -28.0 0.5db 73 1fh -9.0 -29.0 1eh -10.0 -30.0 ::: 09h -31.0 -51.0 08h -32.0 -52.0 1db 24 07h -34.0 -54.0 06h -36.0 -56.0 05h -38.0 -58.0 04h -40.0 -60.0 2db 4 03h -44.0 -64.0 02h -48.0 -68.0 01h -52.0 -72.0 4db 3 00h mute mute 1 table 11 . input gain setting ipgl and ipgr are read by up current values at rising of cs pin. these registers are reset by pd pin="l", then inhibits writing to these registers. these registers are reset by pm0="0".
asahi kasei [ak4516a] m0026-e-00 1998/08 - 32 - auto recovery control auto recovery operation starts after completing auto limitter operation (lcdet="1") at lmte=rcve="1". ipga gain increases automatically by this operation up to the set reference level(ref6-0). then the ipga value is set for l/r commonly. either zero crossing or fs(sampling frequency) period for this auto recovery operation is decided by zero crossing detection at the auto recovery operation and the writing operation by up (=zenm). during the auto recovery operation, when either input signal level of lch or rch exceeds the auto limitter detection level (lmth1-0), the auto recovery operation changes into the auto limitter operation immediately. (refer to figure 9 ) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ch auto recovery control 1 0 0 0 0 wtm1 wtm0 ratt1 ratt0 r/w rd rd rd rd r/w r/w r/w r/w reset 00001000 wtm1-0: auto recovery waiting time recovery operation is done at a period set by wtm1-0 when any limitter operation does not occur at full-auto mode. when the input signal level exceeds auto recovery waiting counter reset level set by lmth1-0, the auto recovery waiting counter is reset. the waiting timer starts when the input signal level becomes below the auto recovery waiting counter reset level. when the auto recovery waiting time(wtm1-0) is shorter than zero crossing timeout period of the auto recovery operation(nrtm1-0), the auto recovery is operated by nrtm1-0. therefore, in this case the auto recovery operation period is not constant. timeout wtm1 wtm0 48khz 44.1khz 32khz 0 0 512/fs 10.7ms 11.6ms 16.0ms 0 1 1024/fs 21.3ms 23.2ms 32.0ms 1 0 2048/fs 42.6ms 46.4ms 64.0ms reset 1 1 4096/fs 85.2ms 92.8ms 128.0ms table 12 . auto recovery operation waiting period ratt1-0: auto recovery gain step during the auto recovery operation, the number of steps changed from current ipga value is set. for example, when the current ipga value is 30h, ratt1="0", ratt0="1" are set, ipga changes to 32h by the auto limitter operation, the input signal level is gained by 1db(=0.5db x 2). the auto recovery operation period is fs period at zenm="0", the auto recovery operation is done after zero crossing detection or timeout in case of zenm="1" when the ipga value exceeds the reference level (ref6-0), the ipga value does not increase. ratt1 ratt0 gain step 0 0 1 reset 01 2 10 3 11 4 table 13 . auto recovery gain step setting
asahi kasei [ak4516a] m0026-e-00 1998/08 - 33 - figure 12 . auto recovery operation (lmat=ratt = 1 step, zenm=zelm="1") 1 { after completing the auto limitter operation, the auto recovery operation wait for only a period set by wtm1-0. if the auto limitter operation is not occurred during the recovery operation, the auto recovery operation is done only once. 2 { ipga is changed by zero crossing in the auto recovery operation, and the count of the next recovery waiting period is also proceeding at the same time. 3 { when the auto limitter operation is entered in zero crossing waiting(rch), the auto recovery operation in progress is stopped, the auto limitter is done according to smaller value (rch in the figure 10) of the ipga value. then, ipgl is changed from 30h to 2eh and ipgr is changed from 2fh to 2eh. (refer to recovery operation 1) 4 { when the auto recovery operation is waiting for the next operation, the limitter operation is done from ipga value at that time . (refer to recovery operation 2) this register is reset by pd pin = "l", then inhibits writing to this register.
asahi kasei [ak4516a] m0026-e-00 1998/08 - 34 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0dh auto recovery control 2 0 ref6 ref5 ref4 ref3 ref2 ref1 ref0 r/w rd r/w r/w r/w r/w r/w r/w r/w reset 00110000 ref6-0: set the reference value at auto recovery operation during the auto recovery operation, when ipga value becomes the reference value set by ref6-0, the gain of the auto recovery operation does not exceed the reference value. the reference value is set commonly as for lch and rch. during the auto recovery operation, if ipga value exceeds the setting reference value by gain operation, ipga does not become the larger than the reference value. for example, when ref=30h, ratt=2 step, ipga=2fh, ipga will become 2fh + 2step = 31h by auto recovery operation, but ipga value becomes 30h as ref value is 30h. ipga should be certainly set to the same value or smaller than ref value before entering full-auto mode . gain(db) data mic line step level 68h +28.0 +8.0 67h +27.5 +7.5 66h +27.0 +7.0 ::: 30h 0.0 -20.0 2fh -0.5 -20.5 ::: 21h -7.5 -27.5 reset 20h -8.0 -28.0 0.5db 73 1fh -9.0 -29.0 1eh -10.0 -30.0 ::: 09h -31.0 -51.0 08h -32.0 -52.0 1db 24 07h -34.0 -54.0 06h -36.0 -56.0 05h -38.0 -58.0 04h -40.0 -60.0 2db 4 03h -44.0 -64.0 02h -48.0 -68.0 01h -52.0 -72.0 4db 3 00h mute mute 1 table 14 . reference value setting in auto recovery operation these bits are reset by pd pin ="l", then inhibits writing to these bits.
asahi kasei [ak4516a] m0026-e-00 1998/08 - 35 - system design figure 13 shows the system connection example. an evaluation board [akd4516a] is available which demonstrates the optimum layout, power supply arrangement and measurement results. figure 13 . typical connection diagram note: - lrck=fs, sclk 3 32fs or 64fs, mclk=256fs or 384fs - power supply lines of va and vd should be distributed separately from the point with low impedance of regulator or connecting to the resistor of 10 ohms. - when lout(rout) drives some capacitive load, some resistor should be added in series between lout(rout) and capacitive load. - the capacitor value on vcom depends on low frequency noise level of power supply.
asahi kasei [ak4516a] m0026-e-00 1998/08 - 36 - 1. grounding and power supply decoupling the ak4516a requires careful attenuation to power supply and grounding arrangements. when va and vd are supplied separately, va should not be the higher voltage than vd. if so not, va is supplied from analog supply in system and vd is supplied from va via 10 ohms resistor.(refer to figure 13 ) system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the ak4516a as possible, with the small value ceramic capacitor being nearest. 2. voltage reference vcom is a signal ground of this chip. an electrolytic less than 4.7uf in parallel with a 0.1uf ceramic capacitor attached to these pins eliminates the effects of high frequency noise. no load current maybe drawn from vcom pin. all signals, especially clock, should be kept away from the va, vcml, vcmr, vcom pins in order to avoid unwanted coupling into the ak4516a. 3. analog inputs adc inputs are single-ended and internally biased to vcml & vcmr with 50k w (typ). the input signal range scales with the supply voltage and nominally 0.57 x va vpp(typ). the adc output data format is 2's compliment. the output code is 7fffh(@16bit) for input above a positive full scale and 8000h(@16bit) for input below a negative full scale. ideal code is 0000h(@16bit) with no input signal. 4. analog outputs the analog outputs are also single-ended and centered around the vcom voltage. the input signal range scales with the supply voltage and nominally 0.6 x va vpp(typ). the dac input data format is 2's compliment. the output voltage is a positive full scale for 7fffh(@16bit) and a negative full scale for 8000h(@16bit). the ideal output is vcom voltage for 0000h(@16bit). if the noise generated by the delta-sigma modulator beyond the audio band would be the problem, the attenuation by external filter is required.
asahi kasei [ak4516a] m0026-e-00 1998/08 - 37 - package z z z z 24pin vsop (unit: mm) ? material & lead finish package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder plate note: dimension * does not include mold flash.
asahi kasei [ak4516a] m0026-e-00 1998/08 - 38 - marking contents of aaxxxx aa: lot# xxxx: date code
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